In logic devices such as finFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize ...

Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce the ...

the scaling of silicon-based metal-oxide-semiconductor field-effect transistors (Si MOSFETs) and evolution of novel structure transistors in accordance with Moore’s Law, especially for modern ...

Two distinct structures have been developed for the enhancement mode of GaN-based high-electron–mobility transistors (HEMTs). These two modes are the metal-insulator–semiconductor (MIS) structure, 2 ...

A research team has implemented a novel method to achieve epitaxial growth of 1D metallic materials with a width of less than 1 nm. The group applied this process to develop a new structure for 2D ...

A lot of researchers are out there working to put an end to the "silicon" in Silicon Valley. That is, they're looking for an electronics material that both conducts electricity better and allows for ...

A team of scientists from the Institute for Basic Science has developed a revolutionary technique for producing 1D metallic materials with a width of less than 1 nm by epitaxial growth. Using this ...